Bit-Slicing in Cadence

Bit-Slicing in Cadence
Evan Vaughan
No native support for bit-slicing in Cadence Synthesis ToolsSynopsys does provide thisTrick RTL Compiler and Soc Encounter into laying out and Adder in a bit sliceUse 4 bitKogge-Stone adder as test design
What I’m Trying to Do
ReduceNangatelibrary to only necessary componentsand, or, inv,xor, aoi21Very disorderedlayout
Initial Synthesis
Initial Synthesis Placement
Made no modifications toNangatelibraryWant Generate/Propagate blocks to be in order on, on top row
Second Attempt
Synthesizednetlistcreated 4 different instantiations of a half-adder (GPGenerator) and placed them separatelyI edited synthesizednetlistto have one large instantiation that would be called once.
Third Try
no change.
Create a new library using modifiedNangatecomponentsCombine four half-adder blocks into one large standard cellDetermine what other components can be combined laterRequires layout and schematic views
Fourth (current) Method
Viewing layoutsCouldn’t directly open .oalayouts in virtuosoGot around this by “streaming” GDSII layout versionsSchematicsPNG and .edifviewsBased schematic off PNG, failed LVSCouldn’t import .edifRead through .edifand found thatNangateuses low threshold modelsStill failed LVS (no power or ground connections)
Problems encountered
Because just four blocks combined, can just edit .lib and .leffiles by hand to create new cellsShouldn’t be great performance difference between single block and four combined blocks
Continued….
Questions/Suggestions