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6.175 Final Project Part 0_ Understanding Non-Blocking ...

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6.175 Final ProjectPart 0: Understanding Non-Blocking Caches and Cache Coherency
Answers
Notation
Addresses are ordered triples:(tag, index, offset)Cache lines are addressed with ordered pairs:(tag, index)Cache slots are addressed by indexReading a cache line from memory:M[(tag, index)]
Non-Blocking Cache
Given: Processor requests andmemory responsesAssignment: Complete the following tables (not all cells should be filled)We will focus on Loads first and Stores secondIn later tables we integrate Loads and stores together
Multiple Requests in Flight – Part 1
Multiple Requests in Flight – Part 2
Same Cache Line, Different Offset
Same Index, Different Tag
Stores
Cache can’t acceptReqwhile handling memoryResp
Store Bypassing
Resending Requests
Cache Coherency
Given: Initial cache states for a single address and a cache request for that addressAssignment:Write the rules each module needs to execute to perform the cache requestYou may have to keep track of what messages are still in the message network. Unfortunately there is not enough space to include it in the table.
No Contest: Cache 0 - Ld
Other Cache is Writing: Cache 0 – Ld
Lots of Downgrading: Cache 0 – St
M state for different tag. Need to first evict this line, and then upgrade to M for the desired tag
Bonus: Both want to write
The Rest of the Project – Part 1
Building a non-blocking cache hierarchy and testing with simulated use casesThis includes designing modules for Message FIFOs, the Message Network, the Cache Parent Processor, and the Non-blocking CachesSome of the included tests are identical to the executions shown in Part 0It is important to know what the modules are supposed to do when debugging!
Part 1: Non-Blocking Coherent Cache Summary
Request from processor:IfLdrequest:If inStQ– return dataIf in cache – return dataOtherwise:EnqueueintoLdQSend downgrade response* and upgrade request if possibleIf St request:If cache hit andStQempty – write to cacheOtherwise:EnqueueintoStQSend downgrade response* and upgrade request if possible
*Downgrade responses are not alwaysnecessary
Part 1: Non-BlockingCoherent CacheSummary
Message from Parent:If upgrade response:Update cache lineSearchLdQand return responses until no more hits (multiple cycles)Write to cache for head ofStQuntil cache miss (multiple cycle)Send upgrade to M request for head ofStQ(if possible)Send upgrade to S request forLdQentry with index matching the response (if possible)If downgrade request:Update cache line (if necessary)Send response (if necessary)
The Rest of the Project – Part 2
Integrating the Non-Blocking Cache with an out-of-order processor core to create a multicore SMIPS processorRequires adding support for LL (load-link) and SC (store-conditional) instruction and memory fences.This will also include
The Rest of the Project – Timeline
Part 1:Distributed in waves this weekendFinish before checkpoint meetingsCheckpoint Meetings:Wednesday, December 3rdand Friday, December 5thduring class timeYou will sign up for slots soonPart 2:Distributed around the time of the checkpoint meetingsDue December 10that 3 PM –Strict deadline!Presentations:December 10thfrom 3 PM to 6 PM in 32-D463 (Star)Includes Pizza!

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6.175 Final Project Part 0_ Understanding Non-Blocking ...