Introduction to writing a Test Bench in HDL

Introduction to writing a Test Bench in HDL
MridulaAllani
Spr 2011, Apr 1
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5270/6270 Guest Lecture by M. Allani
What isA Test Bench?
Test Bench is a program that verifies the functional correctness of the hardware design.The test bench program checks whether the hardware model does what it is supposed to do and is not doing what it is not supposed to do.
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Main Functions of a Test Bench
Generate stimulus for testing the hardware block.Apply the stimulus.Compare the generated outputs against the expected outputs.
GeneratingInputStimuli
Design Under Test (DUT)
ComparingGenerated Outputsand ExpectedOutputs
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Generating Stimulus Vectors
Vectors can be generated within the test bench program or generated elsewhere and supplied to the test bench program as an input file.Vectors can also be stored in a table within the test bench program.
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Typical VHDL Test Bench
Generate-stimulus-vectors-using-behavioral-constructs;Apply-to-entity-under-test;DUT:design_under_testportmap(port-associations );Monitor-output-values-and-compare-with-expected-values;if (no errors)report "Testbenchcompleted!"severity note;elsereport "Something wrong!"severity error;end if;endtb_behavior;
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Defining a Vector Table in VHDL
Example,constantno_of_bits: INTEGER := 4;constantno_of_vectors: INTEGER := 5;typetable_typeis array (1 tono_of_vectors) ofmy_vector(1 tono_of_bits);constantvector_period: time:= 100 ns;constantinput_vectors:table_type:=("1001", "1000", "0010", "0000", "0110");signalinputs:my_vector(1 tono_of_bits);signala, b, c: my;signald:my_vector(0 to 1);
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Reading vectors from a ASCII file
Example,processtypevec_typeis file ofmy.vector;filevec_file:vec_typeis in "/usr/example.vec";variablelength: INTEGER;variablein_vector:my_vector(1 to 4);beginlength:= 4; - The number of bits to be read.while (not ENDFILE(vec_file)) loopREAD (vec_file,in_vector, length);- It is necessary to specify thelengthof the vector to be read- since the file contains values of an unconstrained array type.end loop;end process;
Spr 2011, Apr 1
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A Linear VHDL Test Bench
Example,inputs<=input_vectors(1) after 10 ns,input_vectors(2) after 25 ns,input_vectors(3) after 30 ns,input_vectors(4) after 32 ns,input_vectors(5) after 40 ns;a<= inputs(1);b<=inputs(4);c<=inputs(1);d<=inputs(2 to 3);
Spr 2011, Apr 1
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Using a ‘generate’ statement
Example,G1: for J in 1 tono_of_vectorsgenerateinputs<=input_vectors(J) after (vector_period* J);end generate G1;a<= inputs(1);b<=inputs(4);c<=inputs(1);d<=inputs(2 to 3);
Spr 2011, Apr 1
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Using Random Numbers in VHDL
uniform(variableseed1, seed2 :inoutpositive; variable X : out real);1 <= seed1 <= 21474835621 <= seed2 <=2147483398Example,PROCESSVARIABLEseed1, seed2: positive;-- Seed values for random generatorVARIABLErand: real;-- Random real-number value in range 0 to1.0VARIABLEint_rand: integer;-- Random integer value in range 0..4095VARIABLEstim:std_logic_vector(31DOWNTO 0);-- Random32-bitstimulusBEGINfor i in 1 to 1000 loopUNIFORM(seed1, seed2, rand);-- generate random numberint_rand:=INTEGER(TRUNC(rand*256.0));--Convert to integer in range of 0 to 255--,findintegerpartstim:=std_logic_vector(to_unsigned(int_rand,stim'LENGTH));--convert to--std_logic_vectorend loop;
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Librariesneeded
use ieee.std_logic_1164.all;useieee.std_logic_textio.all; --For file operationsuseieee.numeric_std.all; --For unsigned numbersuseieee.math_real.all;--For random number generationusestd.textio.all;
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Simple Example in VHDL
-- test case 1wait for 10 ns;assert (T_Q=1)report "Failed case 1" severity error;if (T_Q/=1) thenerr_cnt:= err_cnt+1; end if;-- test case 2wait for 10 ns;assert (T_Q=2)report "Failed case 2" severity error;if (T_Q/=2) thenerr_cnt:= err_cnt+1; end if;if (err_cnt=0) thenassert falsereport "Testbenchof Adder completed successfully!" severity note;elseassert truereport "Something wrong, try again" severity error; end if;wait;end process;end TB;
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Typical Verilog Test Bench
initialbegin$dumpfile(“dump.vcd");$dumpvars;endinitialbegin$display(“variable list with their typespecifier”);$monitor(“variable list with their typespecifier”);endinitial#simulation_time$finish;//Rest oftestbenchcode after this lineendmodule
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Defining a Vector Table in Verilog
Example,no_of_bits=4;no_of_vectors= 5;reg[0 : (no_of_vectors-1)]table[0: (no_of_bits-1)];vector_period= 100 ns;table[0]= 4’b1001;table[1]=4’b1000;table[2]=4’b0010;table[3]=4’b0000;table[4]=4’b0110 ;
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Example,vec_file=$fopen("/usr/example.vec“);results= $fopen("/usr/results .dat");reg[3:0]my_vectorlength[0:3] ;//The number of vectors and number of bits to be read for each vector.c = $fgetc(file);while(c !== `EOF)begin$readmemh(“vec_file”, length);//Readhex file content into a memory array.$readmemb(“vec_file”, length);//Readbinary file content into a memoryarray.$fdisplay(results, variable list with formatspecifiers);$fmonitor(results,variable list with formatspecifiers);$fclose(results);$fclose(vec_file);endend process;
Reading vectors from a ASCII file
Spr 2011, Apr 1
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A Linear Verilog Test Bench
Example,#10nsinputs=input_vectors(1);# 25 nsinputs=input_vectors(2);# 30 nsinputs=input_vectors(3);# 32 nsinputs=input_vectors(4);# 40 nsinputs=input_vectors(5);a = inputs[1];b=inputs[4];c=inputs[1];d=inputs[2 : 3];
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Example,generategenvarj;for (j=0;j<=no_of_vectors; j=j+1)beginvector_period= (vector_period* j);#vector_periodinputs=input_vectors(j); endendgeneratea = inputs[1];b=inputs[4];c=inputs[1];d=inputs[2 : 3];
Using a ‘generate’ statement
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Using Random Numbers inVerilog
Example 2,moduleTb();integeradd_2,add_3;reg[31:0] add_1;initialbeginrepeat(5)begin#1;add_1 = $random % 10;add_2 = {$random} %10 ;add_3 = $unsigned($random) %10 ;endendinitial$monitor("add_3 = %d;add_2 = %d;add_1 = %d",add_3,add_2,add_1);endmoduleRESULT:add_3 = integers between 0 and 10add_2 = integers between 0 and 10add_1 = the result will not be an integer between 0 and 10 because $random also generates some negative 32-bit numbers.In general,min + {$random} % (max - min )will generate random numbers between min and max.
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Simple Example inVerilog
//=====vector generation=========#50 a = 2'b00; b = 2'b01; #50 a = 2'b00; b = 2'b10;#50 a = 2'b00; b = 2'b11;end//=====display=====always @(a or b orcarryin)$display ("time=%t", $time, "carryin=%b",carryin, "a=%b", a, "b=%b", b, "carryout=%b", carryout, "sum=%b", sum);//======job control=====initialbegin#10001 $finish;endendmodule
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References
A VHDL Primer, 3rd Edition,J.Bhaskarhttp://testbench.in/http://www.eng.auburn.edu/~strouce/class/elec4200/TestBench.pdfhttp://www.synthworks.com/downloads/ConstrainedRandom_SynthWorks_2009.pdfhttp://esd.cs.ucr.edu/labs/tutorial/http://www.markharvey.info/vhdl/rnd/rnd.htmlhttp://www.questatechnologies.com/VHDLTestbenchGenerator.htmlhttp://www.xilinx.com/itp/xilinx8/books/data/docs/xst/xst0086_10.html
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